Forum Discussion

gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
6 years ago

Error related to defparam in Qsys system containing Nios

​I am trying to simulate a Qsys system containing Nios II and custom Qsys peripherals. I am using Quartus 18.0 and ActiveHDL 10.5a. The error that shows up at start of simulation is:

# ELAB2: Fatal Error: ELAB2_0093 The defparam statement from module "SPRINT_SYS_NiosII_cpu_register_bank_a_module" in "/T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a" points to variable "address_reg_b" in a non-Verilog design region "/T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a/the_altsyncram".
# ELAB2: Last instance before error: /T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a
# KERNEL: Error: E8005 : Kernel process initialization failed.
# VSIM: Error: Simulation initialization failed.

It is not clear what this actually means. The SPRINT_SYS is the name of the Qsys system.

2 Replies

  • gyuunyuu's avatar
    gyuunyuu
    Icon for Contributor rankContributor
    6 years ago

    ​It seems that this error occurs because VHDL version of altsyncram is being instantiated in Verilog code of the Nios and passing defparam to generic does not seem to be working correctly.

    The altsyncram is defined inside two places altera_mf.v and altera_mf.vhdl. My testbench compiles the VHDL variant. If I compile the Verilog variant then this error goes away.

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    6 years ago
    Good to hear that, some of the IP need to use verilog code. The VHDL variant is not supported for some IP