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Ah-ha, thanks! I was not doing that.
So - another question - try to run the timing analysis, and get this:
Error: Can't run Timing Analyzer (quartus_tan) -- Fitter (quartus_fit) failed or was not run
What/where is the "fitter?" ???
Thanks again!
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Hi,
sorry my fault.
In order to run the timing analyzer you have to perform a complete run, which includes:
1. Analysis & Elaboration
Your HDL is analyzed , the Hierachy is extratcted etc.....
2. Synthesis
Your design is converted in Logic, Register ....
3. Mapping
Your design is mapped to FPGA resource like LUT's, DSP Blocks ....
4. Fitter
Your design is placed and routed
5. Timing Analysis
After Place&Route you can analysis the real timing of your design
That all you need to put your design in the FPGA.
Kind regards
GPK
Honored Contributor
