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Altera_Forum's avatar
Altera_Forum
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10 years ago

Error loading design in Modelsim

Hello,

I have an issue regarding modelsim, I'm using altera 11.1 version and modelsim is 6.4a starter edition.When I synthesis the ddr3 design in altera and try to simulate in modelsim then i'm facing error such as instantiation of ddr3 failed.. but the IP core is present.

The error message is shown below

# ALTERA version supports only a single HDL# ** Error: (vsim-3039) D:/2015/July/AS_RU_Application/Source/RTL/ddr3_interface/ddr3_interface_test.vhd(257): Instantiation of 'ddr3' failed.# Region: /ddr3_interface_test# Error loading design

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Well there is your problem. The altera version of modelsim only support single language simulation.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Ya thank you I figured it out. this modelsim doesn't support mixed language.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Can you suggest me which version in modelsim supports mixed language so that i can use it in my design.. as the top level designs are in vhdl but the core designs and some other files are in verilog.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Can you suggest me which version in modelsim supports mixed language so that i can use it in my design.. as the top level designs are in vhdl but the core designs and some other files are in verilog.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, I have a licensed version of modelsim designer6.4d where I'm facing another problem such as given below.. The mixed language issue is resolved.

    # 0# Fatal error in Process line__10895 at C:/altera/11.0sp1/quartus/eda/sim_lib/altera_mf.vhd line 11063# # HDL call sequence:# Stopped at C:/altera/11.0sp1/quartus/eda/sim_lib/altera_mf.vhd 11063 Process line__10895#
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    I'm having the same problem with simulating DDR3.

    Did you find a solution?

    # Fatal error in Process line__10895 at C:/altera/11.0/quartus/eda/sim_lib/altera_mf.vhd line 11063# # HDL call sequence:# Stopped at C:/altera/11.0/quartus/eda/sim_lib/altera_mf.vhd 11063 Process line__10895