error in verilog code

The code is simply doing nothing, because the output pwm isn't set anywhere in the code. Synthesizes to nothing (0 LEs).

module pwm1(clk,pwm);
input clk;
output pwm;
reg counter=0;
reg pwm;
always @(posedge clk)
begin
  counter=counter+1;
  If (counter<=256) 
    counter=0;
end
endmodule

sorry sir , I don't mean about pwm generation. I want to know why error occurring during compilation of attached code.

Verilog is case sensitive, if isn't a legal keyword.

Thank you sir