error in verilog code

The code is simply doing nothing, because the output pwm isn't set anywhere in the code. Synthesizes to nothing (0 LEs).

A complete pwm unit would have a duty cycle input.

if (counter<=256) should be changed to if (counter >= 255) for reasonable counter operation.

module pwm1(clk,pwm);
input clk;
output pwm;
reg counter=0;
reg pwm;
always @(posedge clk)
begin
  counter=counter+1;
  If (counter<=256) 
    counter=0;
end
endmodule