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Altera_Forum
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15 years ago

Error in Synthesis of ddr3 controller with a NiosII on StratixIV

Hi, I am getting the following error while running for StartixIV using Qaurtus2 9.1: error: the datain input of delay chain primitive "altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Well...it turns out that it was a signal tap error. so I worked around it by removing the dq, dqs, dqsn and dm signals from signal tap. I then added the internal signals pointing to these signals to signal tap and it synthesized well. Also, there was another problem:-

I was running all the tcl scripts before analysis and synthesis. Make sure to run only pin_assignment.tcl and the ddr_phy tcl script and "do not run" the auto_detect_pins tcl.

-Sid