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Altera_Forum's avatar
Altera_Forum
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11 years ago

Error during Flash based system compilation

Hi there ,

I am about to design an external memory ( flash ) based system , here i give the Qsys design , but during quartus compilation i got these errors , attached text file

hope some help

thanks in advance :)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Two lines of the trace give me a clue but not how to solve it:

    --- Quote Start ---

    Warning (10230): Verilog HDL assignment warning at altera_merlin_width_adapter.sv(958): truncated value with size 24 to match size of target (8)

    --- Quote End ---

    and:

    --- Quote Start ---

    Error (10198): Verilog HDL error at altera_merlin_width_adapter.sv(433): part-select direction is opposite from prefix index direction

    --- Quote End ---

    Each of these suggest things may not be connected up as intended. How are you instantiating your qsys module? It looks like "off_chip_mem" is your top level Qsys entity - right? So, you're just throwing your generated Qsys output at Quartus - no higher level vhdl module...?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi a_x_h_75 !

    Sorry for being late to reply , so much work since then , in any way you are right i didn't code a top level entity , i thought set as top level entity is enough :rolleyes: ,

    I am working on it for the moment .

    Just a question why set as top entity tool didn't work , i am working on Quartus 13.1 , and have added the .qip file and then right click set as top entity ?

    thanks a lot , (thought that none would dare read the .txt error file , but you did "My respect !!")