Error: Can't synthesize current design -- Top partition does not contain any logic

Study the analysis and synthesis messages. Most likely you have lots of messages about logic getting removed. Start at these. There will also be sections of the report on removed nodes that triggered other things being removed. This is caused by having something necessary incorrectly tied off(like a clock or reset). This is somewhat strange to occur in your top-level, since you don't actually connect your top-level ports, they just go to pins. Most likely it's at a lower-leve hierarchy where a clock or something isnt' tied up, all that logic gets removed, and due to reductions, everything else gets removed.