error: cannot synthesize non-constant real objects or values

Hi,

I used the code below to create a block that generates a random signal at the output with quartus ii:

----------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.math_real.ALL; -- for UNIFORM, TRUNC functions

USE ieee.numeric_std.ALL; -- for TO_UNSIGNED function

ENTITY tri_state_buffer_1 IS

PORT

(

--oe_input_name : IN STD_LOGIC;

--data_input_name : IN STD_LOGIC;

sNoise : buffer STD_LOGIC

);

END tri_state_buffer_1;

ARCHITECTURE arch_tri_state_buffer_1 OF tri_state_buffer_1 IS

BEGIN

PROCESS

VARIABLE seed1, seed2: positive; -- Seed values for random generator

VARIABLE rand1 : real; -- Random real-number value in range 0 to 1.0

VARIABLE seed3, seed4: positive; -- Seed values for random generator

VARIABLE rand2 : real; -- Random real-number value in range 0 to 1.0

VARIABLE width: time; -- noise pulse width

VARIABLE interval: time; -- noise interval

BEGIN

seed1 := 7;

seed2 := 1;

seed3 := 8;

seed4 := 5;

LOOP

UNIFORM(seed1, seed2, rand1);

UNIFORM(seed3, seed4, rand2);

width := (rand1*0.00000001)*1 sec;

interval := (rand2*0.0000001)*1 sec;

Wait FOR width;

sNoise <= NOT(sNoise);

Wait FOR interval;

sNoise <= NOT(sNoise);

END LOOP;

END PROCESS;

END arch_tri_state_buffer_1;

----------------------------------------------------------------------------

When I click "create symbol" there is no error and warning.

But, when I use it in schematic and compile, I receive below errors:

Error (10414): VHDL Unsupported Feature error at tri_state_buffer_1.vhd(17): cannot synthesize non-constant real objects or values

Error (10442): VHDL Process Statement error at tri_state_buffer_1.vhd(16): Process Statement must contain either a sensitivity list or a Wait Statement

Error (12152): Can't elaborate user hierarchy "tri_state_buffer_1:inst"

!