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So what is the purpose of it at all?
Why to simulate something that is not synthesised ?
Let me check that i understood correct, there is no float in VHDL? Is there any way to :
count <= count + 0.0001;
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Because you may want to use real values as part of some model, or to calculate constant values, or generate random numbers in your testbench.
If count is declared as real, then your statement is perfectly valid VHDL - you just cannot synthesise it for an FPGA.
If you want to do floating point synthesised code, you'll need to use the floating point IP cores that are available in the IP catalog in quartus. The signals used here will be std_logic_vectors. Or if you want to be adventurous, you could use the float_pkg available in VHDL 2008.
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