Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
How did you fix it?
I'm getting the same error on my De1-Soc board and can't figure out how to fix it. - Altera_Forum
Honored Contributor
It just maybe your design is too big for the FPGA. One other solution is to try and recompile with the --high-effort flag and see.
- Altera_Forum
Honored Contributor
You can see the source usage estimation in the acl_quartus_report.txt file 。you can also refer to the log file under the project file folder bin_nameofkernel.