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PWang61's avatar
PWang61
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3 years ago

Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10

I am trying SSS communication with Intel® Cyclone® 10 LP FPGA Evaluation Board. https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/10-lp-evaluation-kit.html T...
PWang61's avatar
PWang61
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3 years ago

@AR_A_Intel Thanks for your reply. I will send you all files.

ms71's avatar
ms71
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1 year ago

Hi,

i have the same issue.

May i get the files to.

I like to play around with Cyclone 10 "golden_system_ref_design"

Info (12021): Found 1 design units, including 1 entities, in source file db/ip/q_sys/submodules/q_sys_user_dipsw.v
Info (12023): Found entity 1: q_sys_user_dipsw
Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_Opencore_edition (AE7C_000E) in current license.
Error (10003): Can't open encrypted VHDL or Verilog HDL file ".../fpga/c10/dl/cyclone10lp-10cl025yu256-eval-v17.0.0stdb595/cyclone10LP_10cl025yu256_eval_v17.0.0stdb595/examples/golden_system_ref_design/golden_system_ref_design/db/ip/q_sys/submodules/sll_ca_hbc_t001_top_enc.v" -- current license file does not contain a valid license for encrypted file