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The link to your code is broken, but the error is saying that you can implement the multiplier using logic instead of a DSP block, but you can't use synchronous clear for the multiplier in this implementation. Without seeing the code, it's not clear why, but this may be an architecture limitation of the Cyclone V device.
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Just in case it breaks again, here's my code:
module pipemult(
clk1,
wren,
dataa,
datab,
rdaddress,
wraddress,
q
);
input clk1;
input wren;
input [7:0] dataa;
input [7:0] datab;
input [4:0] rdaddress;
input [4:0] wraddress;
output [15:0] q;
reg [15:0] q;
wire [15:0] mult_to_ram, ram_out;
// Insert multiplier instantiation here
ram ram_inst
(.clock(clk1),
.wren(wren),
.data(mult_to_ram),
.rdaddress(rdaddress),
.wraddress(wraddress),
.q(ram_out));
mult mult_inst(
.clock(clk1),
.dataa(dataa),
.datab(datab),
.result(mult_to_ram));
always @ (posedge clk1)
q <= ram_out;
endmodule
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