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Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
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Altera_Forum
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8 years ago

Review the "MAX 10 FPGA Signal Integrity Design Guidelines", particularly paragraph "Guidelines: Clock and Data Input Signal for MAX 10 E144 Package".

Enter the Toggle_Rate in Pin Planner, the column must be possibly enabled before in context menu:

https://www.alteraforum.com/forum/attachment.php?attachmentid=15198

or enter a tcl command

"set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to clk_1m"