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Rajender1's avatar
Rajender1
Icon for New Contributor rankNew Contributor
2 years ago

Error (174068) DDR3 IP

Hi, I tried to instantiate DDR3 memory IP using Verilog HDL, TSW14J56EVM and Quartus Prime Standard edition software. During Compilation I am encontering an error as mentioned below: Error (174068)...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Rajender,


Have you run *p0_pin_assingments.tcl script after synthesis compilation?

This tcl script will help to setup the pin setting for the UNIPHY IP.


Regards,

Adzim