Forum Discussion
Hi Raj,
I was trying to understand the problem, You have generated a IP using HLS, integrated it in top module and trying to assign a pin which gives you error? Am i right?
We have tried the same with the simple add example for which .IP/.QSYS file is created using HLS and we have used Quartus 17.1 std for integration to top module and assigned a clock pin to AF14 for Cyclone V device 5CSXFC6D6F31C8ES. Attached cmd log and image.
I was not-able to successful replicate the Error mentioned.
However if you can share your .cpp file i can try from my side.
And can you remove the pin assignments and check if fitter is able to place the design successfully with its default assignments
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand Raj Shankar