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Altera_Forum's avatar
Altera_Forum
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15 years ago

Error (10822): HDL error at XXX: couldn't implement registers for assignments

hello everyone

i am having problems with this peice of code

process (clk)

begin

if rising_edge (clk)

then

en<='1';

else en<='0';

end if;

end process;

i have read about thuse errors on the web and saw that the problem is that i cant change the register on both rising edge and falling adge (that would be the ELSE)

but i cant find another way to get the output needed without it.

someone has an idea?

Thanks,

Pini

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    There is no "else" for a register, it only changes its value at the rising_edge of clock (or on an asynchronous reset)!

    You should have an signal that is fed by logic (also known as "cloud") that is stored in a register at rising_edge(clk).

    Actually your register is only '1' for one delta cylce in which we have a rising_edge else it is '0'. In other words it is always '0'.

    you can actually (theoretically) change registers on falling_edge(clk) too, but I don't know what it synthizes:

    if rising_edge(clk) or falling_edge(clk)

    .....

    endif;

    I recommend reading VHDL tutorials and lecture notes.

    But go ahead, it's fun!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your fast answer, It helped.

    i managed to keep the system working with a square signal instead of those deltas, and now qurtus is ok.

    have a good day

    Pini Sberro