Altera_Forum
Honored Contributor
9 years agoError (10759): Verilog HDL error... -> is Verilog-2001 not supported?
Hi All,
I'm receiving the "Error (10759): Verilog HDL error at rly.v(18): object rl_sck declared in a list of port declarations cannot be re-declared within the module body" on the following code:
module rly
(//** System
input clk,
input rstn,
output rl_sck,
);
//////////////////////////////////////////////////////////////////////
//* DECLARATIONS
//////////////////////////////////////////////////////////////////////
reg rl_sck;
endmodule
why this is an error? This is actually a legal verilog-2001 syntax. This module is defined as SystemVerilog HDL file in Quartus-II. Thank you!