Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

error 10559 VHDL

Hi, I was wondering if anyone can shed some light on this error that I managed to obtain. Error (10559): VHDL Subprogram Call error at user_functions.vhd(100): actual for formal parameter...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

To elaborate a bit about the problem, the only case where a register in a subprogram can be synthesized is a construct like below. But it won't work for a counter because the out port can't be read inside the procedure. 

procedure ff (
  signal clk: in std_logic;
  signal d : in std_logic;	
  signal q : out std_logic) is
begin
  if rising_edge(clk) then
    q <= d;
  end if;	 
end;