Forum Discussion
Error 10500: VHDL Syntax
I am working on a code for a basic vending machine that will give out a product at 75cents
BUt for some reason I dont know how to fix this syntax error
Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
Port (
Clock :IN std_logic;
Reset_n :IN std_logic;
Quarter_in :IN std_logic;
Dime_in :IN std_logic;
Nickel_in :IN std_logic;
Pennny_in :IN std_logic;
Coin_Return :IN std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter: std_logic_vector(25 downto 0);
Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money: std_logic_vector(6 downto 0);
Signal Red_Bull: std_logic;
Signal Change_Back: std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
Begin
If reset_n = '0' Then
Int_counter <= (Others => '0');
Elsif (rising_edge(clock)) Then
If int_counter = MAXVALUE Then
int_counter <= (Others => '0');
Else
int_counter <= int_counter + '1';
End If;
End If;
End Process;
Sync:Process (clock, reset_n)
Begin
If (reset_n = '0')then
Current_state <= Wait1;--Wait1 is the default state_type
Elsif(rising_edge(clock))Then
If (int_counter = MAXVALUE)Then
Current_state <=next_state;-- Advance the state(Red Bull)machine
End If;
End If;
End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
Begin
If (int_counter = MAXVALUE) Then
Case(current_state)is
When wait1=>
If (money = "0000000")Then -- No money in vending machine
next_state <= Wait1;
If (Quarter_in = '1')Then -- Money is inserted
next_state <= Quarter;
If (Dime_in = '1')Then
next_state <= Dime;
If (Nickel_in = '1')Then
next_state <= Nickel;
If (Pennny_in = '1')Then
next_state <= Penny;
If (money >= "1001011")Then
next_state <= Enough;
If(Coin_Return = '1')Then
next_state <= Change;
Else
next_state <=Wait1;
End If;
----------------------------------------------------------------- After Quarter Inserted, next step
When Quarter =>
Next_state <= Wait1;
----------------------------------------------------------------- After Dime Inserted, next step
When Dime =>
Next_state <= Wait1;
----------------------------------------------------------------- After Nickel Inserted, next step
When Nickel =>
Next_state <= Wait1;
----------------------------------------------------------------- After Penny Inserted, next step
When Penny =>
Next_state <= Wait1;
When Enough =>
If (money >= "1001011")Then
Next_state <= Excess;
Else
Next_state <= vend;
End If;
When Excess =>
Next_state <= vend;
When vend =>
Next_state <= Wait1;
When Change =>
Next_state <= Wait1;
When OTHERS =>
next_state <= Wait1;
End Case;
End If;
End Process;
----------------------------------------------------------------- Money calculation
Money_Calc:Process(Current_state, money)
Begin
Case (current_state) is
When wait1 =>
Money <= Money;
When Quarter =>
Money <= Money + "0011001";
When Dime =>
Money <= Money + "0001010";
When Nickel =>
Money <= Money + "0000101";
When Penny =>
Money <= Money + "0000001";
When Enough =>
Money <= money;
When Excess =>
Money <= Money;
When vend =>
Money <= Money - "1001011";
When change =>
Money <= "0000000";
When OTHERS =>
Money <= Money;
End Case;
End Process;
End Behavior;
The errors I am getting are Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 12.0 Build 178 05/31/2012 SJ Full Version Info: Processing started: Wed Oct 31 15:32:29 2012 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab06 -c Lab06 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 2 design units, including 1 entities, in source file hex_display.vhd Info (12022): Found design unit 1: Hex_Display-Structure Info (12023): Found entity 1: Hex_Display Error (10500): VHDL syntax error at Lab06.vhd(108) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(111) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(114) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(117) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(120) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(126) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(128) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(130) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(132) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(134) near text "Case"; expecting "if" Error (10500): VHDL syntax error at Lab06.vhd(136) near text "Process"; expecting "if" Error (10500): VHDL syntax error at Lab06.vhd(139) near text "Begin"; expecting ":=", or "<=" Error (10500): VHDL syntax error at Lab06.vhd(162) near text "Process"; expecting "if" Info (12021): Found 0 design units, including 0 entities, in source file lab06.vhd Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings Any assistance would be very helpful.30 Replies
- Altera_Forum
Honored Contributor
In the last process you're using the vector Money like a latch. You have sentences like:
when vend => money <= money - "1001011"; etc. This is not a recommend style of coding for synthesis n a FPGA. A solution may be: process(rst, clk) begin if(rst = '0' ) then money_reg <= ( others => '0' ); elsif(clk'event and clk = '1' ) then money_reg <= money_next; end if; end process; process(Money_reg, ....) begin money_next <= money_reg; case ... is when .... => money_next <= money_reg - "1001011"; ... end case; end process; You create a register for vector Money. - Altera_Forum
Honored Contributor
Can anyone explain me WHY Quartus compiler is so bad? My God... It's one of fewers tools in the Earth to develops digital circuits in FPGA and its have this crap compiler! I just cant imagine... How can Nasa, Darpa and big companies around the world develops something with this crap? Im losing about a couple of hours to solve this mesages, and i cant!
Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if" - Altera_Forum
Honored Contributor
--- Quote Start --- Can anyone explain me WHY Quartus compiler is so bad? My God... It's one of fewers tools in the Earth to develops digital circuits in FPGA and its have this crap compiler! I just cant imagine... How can Nasa, Darpa and big companies around the world develops something with this crap? Im losing about a couple of hours to solve this mesages, and i cant! Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if" --- Quote End --- The Quartus VHDL compiler is actually rather good - you should try the ISE one. It sounds like you have a syntax error near text "case". it is expecting "if". If you want any better help - you'll have to post your code. - Altera_Forum
Honored Contributor
--- Quote Start --- Can anyone explain me WHY Quartus compiler is so bad? My God... It's one of fewers tools in the Earth to develops digital circuits in FPGA and its have this crap compiler! I just cant imagine... How can Nasa, Darpa and big companies around the world develops something with this crap? Im losing about a couple of hours to solve this mesages, and i cant! Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if" --- Quote End --- You can be pretty sure that there's an actual syntax error in your code if Quartus (or any other tool) complains about it. The tool parses the code that you have written, it doesn't attempt to guess what you really mean. It looks like you wrote "end case" where "end if" is expected according to VHDL syntax. Means there's an incomplete if construct that has to be closed first. Regarding scrap compilers, I guess you know the saying "A bad workman always blames his tools" - Altera_Forum
Honored Contributor
Oh sure! I know how works a compiler because i did one, you can see it in this site 52.42.84.20. And yes, i solved this problem and the error was something like that, but i dont remember exactly what i did to solve. I just can't understand how a big company like Altera, now Intel have a compiler so primitive! If you download my compiler, you will see that mesages of error are pretty clear, but i did this in 2 weeks, working 3 hours a day. Why Altera doesnot improved your compiler in all these years? I used this compiler, three years ago, in several projects for embedded computers that i did, in version Quartus 9.1. Today i just was writing a new processor in VHDL to use in neural networks, so i tried use my old Bemicro test kit and i discovered that Altera discontinued the CycloneIII at new compilers! Very good! So i downgrade to Quartus 13.1, that show me the same errors of previous compiler 9.1, so no evolution about that. My complaint is because i like Altera, but i guess that they need improve your tools, because the users dont want lose their time with fool things. They have a computer to solve these fool things, but it is not used for this purpose now, because the compiler is not friendly and smart!
About your phrase, i have another: "A bad company always blames its customers" Thank U Altera GurU! - Altera_Forum
Honored Contributor
--- Quote Start --- Oh sure! I know how works a compiler because i did one, you can see it in this site 52.42.84.20. And yes, i solved this problem and the error was something like that, but i dont remember exactly what i did to solve. I just can't understand how a big company like Altera, now Intel have a compiler so primitive! If you download my compiler, you will see that mesages of error are pretty clear, but i did this in 2 weeks, working 3 hours a day. Why Altera doesnot improved your compiler in all these years? I used this compiler, three years ago, in several projects for embedded computers that i did, in version Quartus 9.1. Today i just was writing a new processor in VHDL to use in neural networks, so i tried use my old Bemicro test kit and i discovered that Altera discontinued the CycloneIII at new compilers! Very good! So i downgrade to Quartus 13.1, that show me the same errors of previous compiler 9.1, so no evolution about that. My complaint is because i like Altera, but i guess that they need improve your tools, because the users dont want lose their time with fool things. They have a computer to solve these fool things, but it is not used for this purpose now, because the compiler is not friendly and smart! About your phrase, i have another: "A bad company always blames its customers" Thank U Altera GurU! --- Quote End --- What exactly is the problem with the altera compiler? You input a load of files, it compiles them, it tells you where your syntax errors are. Isnt that what you need from a compiler? Your problem looked like your poor knowledge of VHDL that was the problem, not the compiler. It also supports 3 languages, and schematics, and can import netlists. It supports many devices, that get very large. It can compile your code into a synthesised netlist, then it will try and fit that netlist onto a chip with 1 million logic elements. This is not some small PLD project, and is NOT a software compiler. Instead of just moaning about something, why not suggest how it can be improved. PS. Nasa et all have no problem with it, because using the altera compiler is usually the last step in the design process. Code will go through verification before it gets to the altera compiler. So engineers will be confident it will actually compile. Syntax errors are the least of their worries (and take very little time compared to everything else). I agree with FvM - your post was little more than a rant from someone who got angry they couldnt work something out for themselves, so blamed the Altera compiler instead. Altera are always good at responding to support requests. Altera do not post on their forums - this is meant for engineers who use altera at work an willing to help others. If you posted an actual question - you'd probably get a better response. - Altera_Forum
Honored Contributor
Tricky,
I thought a new thing now, take note: "Altera (or Intel) needs treat better its customers." I was just trying help you to improve your product, but you are trying attack me. You should thank me for waste my time with it, and if i do that is because i believe that could be better. If you dont like of my comment, just erase it and cancel my account too, i never use this "support" even. And yes, i was angry and wrote that, but because i dont like bad things, and because i dont make bad things. Almost 10k devices that i projected using Altera CPLDs and FPGAs are running around the world, and i did that using AHDL and VHDL. The Altera devices are pretty good, but its compiler is very bad. What happens is with the passing of time using it you just ignore its bad user interface, and adapt yourselve to use. I passed three years without use or coding in Altera tools, so i forgot all tricks to dribble its deficiencies. Specificly about this thread, see the bad mesage of compiler: Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if" Can you see any information about the line of error in this mesage? Yes is (356)! Ok, go there, you found the error? No... Try click on it. What heppened? Nothing? So...how can you help the user like this POOR mesage? I remember how i solved this problem and i will tell you: I broke about 1500 lines of code in 750. I compiled and chose the bad part. I broke again in two parts of 375 and did it again, and again, and again until: "Oh i forgot a semicolon here...". Now tell me: Where is my fault? Have I "poor knowledge of VHDL" like you said just because i forgot a semicolon, or a "end case"? Is It serious? This is just ONE sample but problems like that are in all compiler! I can report you all of this problems, if you want. I am a good user for that because i have a lot of experience using your products, but i lost the vices to correct the compiler deficiencies. Can you help me to help you? Who is the main contact reponsable by Quartus development? I would like show this issue and possibily solutions to him. - Altera_Forum
Honored Contributor
I do not work for altera, neither do most people on this forum. You are not my customer and I was expressing my opinion about how bad your feedback was - it is just abuse with no feedback as to how it can be improved.
These messages are the same in any compiler Ive used, including C, C++, Java, Verilog and system verilog. The line just points to the error - but the source might be miles away and be obscure. If you want to get angry - try doing a testbench in Systemverilog and then work out why your code wont compile. You should raise a support request via the mysupport section of the altera website. Though I think the Quartus VHDL compiler actually comes from Verific : http://www.verific.com/products/vhdl/ I think they also build the compiler for Xilinx. Either way - Ive found all VHDL compilers to give the same errors. - Altera_Forum
Honored Contributor
Ok. if Altera wants repeat the error of all other companies with the same useless messages of error, is fine! All of them are going to wrong way, and all of them will lose customers to other on the shelf solutions, like GPUs, fast processors and something like.
If i could i would a compiler diferent, that help the user to solve the problem, like modern C#, Swift, and Java compilers, because the people are tired to use bad things. See some options that i thought to Altera solve this problems: 1) Each message error you could press F1, to get more details to solve. Today this resorce points to external link on the web thats showing nothing to user. What about change this and put a resume of possibly solutions like we discuss in this forum? Is hard make that? No, it is not. 2)If Altera wants maintain a standard of messages, just to suit some "IEEE" wrong of life. How about make a second set of error messages really usefull? For example, the message of this issue: Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if" Could be a second version like: Error(1): VHDL syntax error in keyword "case" at line xxx, missing a "end case" or Error(2): VHDL syntax error in keyword "if" at line xxx, missing a "end if" Is hard to make that? No, it is not! - Altera_Forum
Honored Contributor
Customers do not chose FPGAs over GPUs because of compilers. Compilers are the least of anyones worries.
They are more interested in the capabilities of the chip. Compilation takes almost no time. It is the design, architecture, simulation, verification that takes weeks, months years. A message that might confuse someone for a few minutes is not going to make someone swap to a GPU after they've already spent months on design and architecture. I think you're overblowing your problem. But feel free to raise a case with altera.