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Altera_Forum
Honored Contributor
14 years agoError 10500: VHDL Syntax
I am working on a code for a basic vending machine that will give out a product at 75cents BUt for some reason I dont know how to fix this syntax error
Library ieee;
Use ieee.numeric_std.all;...
Altera_Forum
Honored Contributor
14 years agoIn the last process you're using the vector Money like a latch. You have sentences like:
when vend => money <= money - "1001011"; etc. This is not a recommend style of coding for synthesis n a FPGA. A solution may be: process(rst, clk) begin if(rst = '0' ) then money_reg <= ( others => '0' ); elsif(clk'event and clk = '1' ) then money_reg <= money_next; end if; end process; process(Money_reg, ....) begin money_next <= money_reg; case ... is when .... => money_next <= money_reg - "1001011"; ... end case; end process; You create a register for vector Money.