Error 10500: VHDL Syntax

In the last process you're using the vector Money like a latch. You have sentences like:

when vend =>

money <= money - "1001011";

etc.

This is not a recommend style of coding for synthesis n a FPGA. A solution may be:

process(rst, clk)

begin

if(rst = '0' ) then

money_reg <= ( others => '0' );

elsif(clk'event and clk = '1' ) then

money_reg <= money_next;

end if;

end process;

process(Money_reg, ....)

begin

money_next <= money_reg;

case ... is

when .... =>

money_next <= money_reg - "1001011";

...

end case;

end process;

You create a register for vector Money.