Error 10346: Formal port or parameter "write" must have a actual or default value

Thanks for your kindly reply.

But the "write" is a 1-bit port! this port doesn't have any parameter defination in the design!

As the design shows bellow:

component syncram

generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;

testen : integer := 0);

port (

clk : in std_ulogic;

address : in std_logic_vector((abits -1) downto 0);

datain : in std_logic_vector((dbits -1) downto 0);

dataout : out std_logic_vector((dbits -1) downto 0);

enable : in std_ulogic;

write : in std_ulogic;

testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none);

end component;