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Altera_Forum
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12 years ago

Error 10327 confusion

Hello.

I am trying to make a simple UP/DOWN counter and I am fairly new to VHDL. I keep getting the following error

"Error (10327): VHDL error at Counter.vhd(51): can't determine definition of operator ""+"" -- found 0 possible definitions"

My code is


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
	generic
	(
	startnum : natural := 0;
	N : natural := 16
	);
	port
	( 
		--Inputs
		EN		:	in std_logic;
		synchr	:	in std_logic;
		asyncr	:	in std_logic;
		dir	:	in	std_logic;			--0 for count down 1 for count up.
		clk	: in std_logic;
		--Outputs
		Y	:	out natural range startnum to n-1
	);
end entity;
architecture counter_v1 of counter is
signal cntconst	:	integer;
begin
process (dir)				--dir in sensitivity list as when this changes we want this process to run.
begin
if (dir = '0') then
	cntconst <= -1; 				--this will count down when added onto to the counter value
end if;
if (dir = '1') then
	cntconst <= 1;
end if;
end process;
process (EN, synchr, asyncr, clk)
variable notsurewhyitworkswiththis	:	integer range startnum to n-1;			--I tried to just use y but for some reason it won't allow that.
begin
if (en = '0') then
else
	if (asyncr = '1') then
		notsurewhyitworkswiththis := 0;
	else
		if (clk = '1') then
			if (synchr = '1') then
				notsurewhyitworkswiththis := 0;
			end if;
	end if;
end if;
if (cntconst < n-1) then
	if (dir = '1') then
		notsurewhyitworkswiththis := notsurewhyitworkswiththis + dir;
	end if;
end if;
if (cntconst > startnum) then
	if (dir = '0') then
		notsurewhyitworkswiththis := notsurewhyitworkswiththis + dir;
	end if;
end if;
end if;
y <= cntconst;
end process;
end counter_v1;
	

It is starting tio get a bit annoying now, I have tried loads of things I read online but to no avail.

Any help would be hugely appreciated.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    dir is a std_logic, and therefore not a number, and notsurewhyitworkswiththis is an integer. The types are incompatible.

  • Altera_Forum's avatar
    Altera_Forum
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    I am being a absolute **** and adding the wrong damn thing. It's meant to be cntconst. Thanks .

  • Altera_Forum's avatar
    Altera_Forum
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    Just to add, your process is not a clocked process. It is using clk as a transparent latch enable. I suggest following the correct template:

    
    process(clk, reset)
    begin
      if reset = '1' then
        --async reset here
      elsif rising_edge(clk) then
        --sync stuff goes here
      end if;
    end process;
    
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thanks, that makes sense.

    It compiled and I did the VWF of it. It has decided not to count...it just stays at 0001 which strikes me as odd as it should be a 16 bit number. Is there anything obvious to you as to why it wouldn't count?
  • Altera_Forum's avatar
    Altera_Forum
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    Open the RTL Viewer to see what Quartus inferred from your code. Post the corrected code. In the original one, the counter enable was used as an asynchronous signal. It should be:

    if( clk'event and...

    if( en = '1' ) then

    count <= count + 1;

    The next state logic was outside the rising edge if. But you may change it. Again, post the code.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I made some changes to it, it is slightly neater now but now it won't compile because it is expecting a bracket or something...error 10500

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity counter is
    	generic
    	(
    	startnum : natural := 0;
    	N : natural := 16
    	);
    	port
    	( 
    		--Inputs
    		EN		:	in std_logic;
    		synchr	:	in std_logic;
    		asyncr	:	in std_logic;
    		dir	:	in	std_logic;			--0 for count down 1 for count up.
    		clk	: in std_logic;
    		--Outputs
    		Y	:	out natural range startnum to n-1
    	);
    end entity;
    architecture counter_v1 of counter is
    signal cntconst	:	integer;
    begin
    process (dir)				--dir in sensitivity list as when this changes we want this process to run.
    begin
    if (dir = '0') then
    	cntconst <= -1; 				--this will count down when added onto to the counter value
    end if;
    if (dir = '1') then
    	cntconst <= 1;
    end if;
    end process;
    process (asyncr, clk)
    begin
        if(asyncr = '1') then
            y < = 0;
        elsif(rising_edge(clk)) then
            if(en = '1') then
                if(dir = '1') then
                    if(y < y'high) then
                        y < = y + 1;
                    end if;
                else
                    if(y > y'low) then
                        y <= y - 1;
                    end if;
                end if;
            end if;
        end if;
    end process;
    end counter_v1;
  • Altera_Forum's avatar
    Altera_Forum
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    if(y < y'high) then

    y < = y + 1;

    end if;

    else

    if(y > y'low) then

    y <= y - 1;

    end if;

    Are y'high and y'low constants? I don't rembember if you can use ' in a signal or constant name ( y'high and y'low ). Replace them by _.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    now it won't compile because it is expecting a bracket or something...error 10500

    --- Quote End ---

    It's really worth to read error messages thoroughly, also reviewing the referred code line.

    --- Quote Start ---

    Error (10500): VHDL syntax error at counter.vhd(39) near text "<"; expecting "(", or "'", or "."

    --- Quote End ---

    y < = 0;

    Did you get an idea why the parser sees a "<" token where you seems to write a "<="? If not, delete and rewrite the line, preferably thinking about required VHDL syntax.

    After fixing this trivial error, Quartus will possibly complain about reading an out signal.