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why not post the actual code rather than post an explination. It could be several things wrong, but it will all come down to VHDL's typing rules.
You did not explain why you are doing what you are trying to do.
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ok, I'm making an easy application of a genethic algorithm with an arbitrary fitness function to select the indivduals(8 bits random unsigned).
The other solution i've tried is the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use Ieee.numeric_std.all;
use work.genetica_type.all;
entity binario_fitness is
Port (
clk : in std_logic;
individuos: in genetica;
adaptacao: out fitness;
somafitness: out unsigned (7 downto 0)
);
end binario_fitness;
architecture Behavioral of binario_fitness is
begin
process (clk)
begin
If (clk 'event and clk = '1') then
for x in 0 to 49 loop
adaptacao(x) <= (individuos(x) and "00000001")-(individuos(x) and "00000010") +(individuos(x) and "00000100")-(individuos(x) and "00001000")+(individuos(x) and "00010000")- (individuos(x) and "001000000") +(individuos(x) and "01000000")-(individuos(x) and "10000000");
somafitness<=(others=>'0');
end loop;
end if ;
end process;
end Behavioral;
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