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Hello,
I'm not sure about all implications of using INTEGER type for bit vectors that represent numbers. It should be stated clearly, that it's possible, including entity ports, also at the top level.
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It should also be noted that if you *do* use integers at the top level you'll need an extra wrapper around any post-synth or post-fit netlists you want to simulate, as they'll end up as logic vectors in the end.
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Cause INTEGER type is only an implicite bit vector, without explicitely defining the bit positions, it could be, that bit operations I'm used to with SIGNED/UNSIGNED could be more complicated or even require type conversion. But I didn't yet try, cause my usage of INTEGER is mainly limited to indexes.
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Also agreed - if you want to do bitwise things, it makes sense to use a vector representation from the start.
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It's been said (I think, in another discussion), that INTEGER usage is shown in most VHDL text books. That is correct so far, as the type and the RANGE syntax are shown, but equivalence to bit vectors isn't discussed necessarily. I was surprized at first look, when I found Uwe Meyer-Baese using INTEGER in many examples in
digital signal processing with fpga. Many people with some knowledge of VHDL think, INTEGER can't be synthesized at all.
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Not helped by the amount of example code which start with
use ieee.std_logic_unsigned.all;
and the use of slv's as unsigned vectors :-)
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Cheers,
Martin
Honored Contributor
