Error 10327: Can't determine definition of operator ""+""

Hello,

I'm not sure about all implications of using INTEGER type for bit vectors that represent numbers. It should be stated clearly, that it's possible, including entity ports, also at the top level. Compile time behaviour could be different, as HDL Guru mentioned. But if only an insignificant effect, this shouldn't determine the design methodology.

The other thing is functionality when designing with parameterized reusable modules. Numerical parameters then always need associated generics defining ranges exept for a few cases, where the range is fixed by design function, e. g. a MAC address having always 32 bit. There is no basic difference with SIGNED/UNSIGNED or INTEGER. With INTEGER, one could try to have parameters, that are either be SIGNED or UNSIGNED, depending on range generics.

Cause INTEGER type is only an implicite bit vector, without explicitely defining the bit positions, it could be, that bit operations I'm used to with SIGNED/UNSIGNED could be more complicated or even require type conversion. But I didn't yet try, cause my usage of INTEGER is mainly limited to indexes.

It's been said (I think, in another discussion), that INTEGER usage is shown in most VHDL text books. That is correct so far, as the type and the RANGE syntax are shown, but equivalence to bit vectors isn't discussed necessarily. I was surprized at first look, when I found Uwe Meyer-Baese using INTEGER in many examples in digital signal processing with fpga. Many people with some knowledge of VHDL think, INTEGER can't be synthesized at all.

As a last remark, VHDL always need type conversion in some places, cause it is so typified. At least when instantiating Altera LPM or IP cores, they are necessary. Some logic functions can't be inferred from HDL, e. g. dividers or dual port RAM with different port widths.

Regards,

Frank