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Altera_Forum
Honored Contributor
Honored ContributorError 10327: Can't determine definition of operator ""+""
Hello to everybody, could someone tell me what's wrong in the following code? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity round16to12 is ...
Altera_ForumHonored Contributor
Honored ContributorHello,
addtion isn't defined for std_logic_vector. You can use explicite numeric types SIGNED or UNSIGNED. Alternatively you can use a library that treats all std_logic_vector as SIGNED or UNSIGNED type: IEEE.STD_LOGIC_SIGNED respectively IEEE.STD_LOGIC_UNSIGNED. Regards, Frank B.T.W: I see this message every time, when I start writing a new component. It's cause VHDL is so strictly typified.
