Error (10293) architecture "fsmd_arch" does not exist for entity "debounce"

Hi everybody, I try to compile a UART test circuit with debounce. But, when I simulate the code, the follow error appear:

Error (10293): VHDL error at uart_teste.vhd(6): architecture "fsmd_arch" does not exist for entity "debounce"

What is wrong in my code???

--############################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity debounce is

port(

clk, reset: in std_logic;

sw: in std_logic;

db_level, db_tick: out std_logic

);

end debounce;

architecture exp_fsmd_arch of debounce is

constant N: integer:=21;

type state_type is (zero, wait0, one, wait1);

signal state_reg, state_next: state_type;

signal q_reg, q_next: unsigned(N-1 downto 0);

signal q_load, q_dec, q_zero: std_logic;

begin

process(clk,reset)

begin

if reset='1' then

state_reg <= zero;

q_reg <= (others=>'0');

elsif (clk'event and clk='1') then

state_reg <= state_next;

q_reg <= q_next;

end if;

end process;

q_next <= (others=>'1') when q_load='1' else

q_reg - 1 when q_dec='1' else

q_reg;

q_zero <= '1' when q_next=0 else '0';

process(state_reg,sw,q_zero)

begin

q_load <= '0';

q_dec <= '0';

db_tick <= '0';

state_next <= state_reg;

case state_reg is

when zero =>

db_level <= '0';

if (sw='1') then

state_next <= wait1;

q_load <= '1';

end if;

when wait1 =>

db_level <= '0';

if (sw='1') then

q_dec <= '1';

if (q_zero='1') then

state_next <= one;

db_tick <= '1';

end if;

else

state_next <= zero;

end if;

when one =>

db_level <= '1';

if (sw='0') then

state_next <= wait0;

q_load <= '1';

end if;

when wait0=>

db_level <= '1';

if (sw='0') then

q_dec <= '1';

if (q_zero='1') then

state_next <= zero;

end if;

else

state_next <= one;

end if;

end case;

end process;

end exp_fsmd_arch;

--#########################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity uart_teste is

port(

clk, reset: in std_logic;

btn: std_logic_vector(2 downto 0);

rx: in std_logic;

tx: out std_logic;

led: out std_logic_vector(7 downto 0);

sseg: out std_logic_vector(7 downto 0);

an: out std_logic_vector(3 downto 0)

);

end uart_teste;

architecture arch of uart_teste is

signal tx_full, rx_empty: std_logic;

signal rec_data, rec_data1: std_logic_vector(7 downto 0);

signal btn_tick: std_logic;

begin

--relacionando com núcleo uart

uart_unit: entity work.uart(str_arch)

port map(clk=>clk, reset=>reset, rd_uart=>btn_tick,

wr_uart=>btn_tick, rx=>rx, w_data=>rec_data1,

tx_full=>tx_full, rx_empty=>rx_empty,

r_data=>rec_data, tx=>tx);

-- relacionando com circuito debounce

btn_db_unit: entity work.debounce(fsmd_arch)

port map(clk=>clk, reset=>reset, sw=>btn(0),

db_level=>open, db_tick=>btn_tick);

-- incrementando loop de dados

rec_data1 <= std_logic_vector(unsigned(rec_data)+1);

-- led display

led <= rec_data;

an <= "1110";

sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111";

end arch;