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CSoti
New Contributor
New ContributorError (10232): Verilog HDL error : index 22 cannot fall outside the declared range [21:0] for vector "address"
I am using Quartus Prime Lite Edition 18.1 to generate a system that includes a Platform designer system with Avalon MM Master-Slave interface. Every time I use more than 2 slaves I get the following...
CSotiNew Contributor
New ContributorProblem resolved and it is a quartus software issue.
The problem was caused by the HDL generated files from platform designer. I changed the option to generate the HDL files from VHDL to Verilog and then in quartus I changed the compiler settings for Verilog input to system verilog.
The problem disappeared. Clearly there is a problem with the avalon MM address space interpretation when generating VHDL files.
Problem solved.
