Error (10232): Verilog HDL error : index 22 cannot fall outside the declared range [21:0] for vector "address"

Problem resolved and it is a quartus software issue.

The problem was caused by the HDL generated files from platform designer. I changed the option to generate the HDL files from VHDL to Verilog and then in quartus I changed the compiler settings for Verilog input to system verilog.

The problem disappeared. Clearly there is a problem with the avalon MM address space interpretation when generating VHDL files.

Problem solved.