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Altera_Forum's avatar
Altera_Forum
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15 years ago

Error (10028): Can't resolve multiple constant drivers for net "P[6]"

below are my code.

when I compile, Error (10028): Can't resolve multiple constant drivers... is coming out, anyone knows what's the problem?

entity DU is

port ( clk, reset, ctrlA, ldA : in std_logic;

ctrlB, ldB, Psel, ldP : in std_logic;

dataA, dataB: in std_logic_vector (3 downto 0);

z, b0 : out std_logic;

P : buffer std_logic_vector (7 downto 0));

end DU;

architecture Structural of DU is

signal Ain, Sum, dataP :std_logic_vector(7 downto 0);

signal A :std_logic_vector(7 downto 0);

signal B :std_logic_vector(3 downto 0);

component reg8 port

(ldP, clk, reset: in std_logic;

data: in std_logic_vector(7 downto 0);

Q : buffer std_logic_vector(7 downto 0));

end component;

component shiftLreg8 port

(d : in std_logic_vector (7 downto 0);

w,clk,reset,ctrlA,ldA: in std_logic;

Q : buffer std_logic_vector (7 downto 0));

end component;

component shiftRreg4 port

(d : in std_logic_vector (3 downto 0);

w, clk, reset, ctrlB, ldB: in std_logic;

Q : buffer std_logic_vector (3 downto 0);

b0 : out std_logic);

end component;

begin

c1: reg8 port map (ldP, clk, reset, dataP, P);

c2: shiftLreg8 port map (Ain,'0',clk,reset,ctrlA,ldA,A);

c3: shiftRreg4 port map (dataB,'0',clk,reset,ctrlB,ldB,B,b0);

Ain <="0000"&dataA;

process (clk,reset)begin

if reset='1' then

A <=(others=>'0');

B <=(others=>'0');

P <=(others=>'0');

elsif (clk'event and clk ='1') then

A <= Ain;

B <= dataB;

P <= dataP;

end if;

end process;

process (Psel) begin

if Psel='1' then dataP <= A+P;

else dataP <= (others=>'0');

end if;

end process;

process (B) begin

if B = "0000" then z <= '1';

else z <= '0';

end if;

end process;

end Structural;

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Besides P also A and B multiple drivers. They are driven in two places, in the first process and in one of the component instances c1-c3. This is like shorting to logic outputs, it's not allowed by VHDL syntax rules. You have to decide, which side is intended to drive the respective nets.