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Altera_Forum
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12 years ago

Error 10028, 10029 Verilog

I'm having a problem with Error 10028 and Error 10029 when i try and compile this in Quartus. I am using Quartus 2 Verilog HDL program language. I also receive this error but I'm hoping when what I'm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I suggest to refer to the Quartus template of a synchronous counter 

always @ (posedge clk or posedge reset)
begin
  if (reset)
    count <= 0;
  else if (enable == 1'b1)
    count <= count + 1;
  end

You are trying to make an asynchronous counter which isn't synthesizable.