Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Error : Powerplay Power Analyzer

I am trying to estimate the power for my design using Power Play Power Analyzer, for that purpose I am using vcd files as input to the power tool to estimate the toggle rate.

My error occured in the middle of the power estimation process and the error details are :

Internal Error: Sub-system: PUTIL_EXTERNAL, File: /quartus/power/putil/putil_library.cpp, Line: 418

(percent >= 0) && (percent <= 100)

Stack Trace:

0x2637 : putil_lib_update_progress_bar + 0x77 (POWER_PUTIL_EXTERNAL)

End-trace

Quartus II Version 8.0 Build 231 07/10/2008 SJ Full Version

Service Pack Installed: 1

I dunno whats the cause of the error but I am assuming that since I am using large vcd file as the input (20GB) quartus is unable to parse the file.

Any help would be much appreciated

22 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    To avoid the timing issues you need to change the settings, do the following steps to change the settings

    1)Assignments > Settings

    2)EDA Tool Settings > Simulation

    3) On the page check Generate VCD file script (optional step)

    4) Go to More Settings on the same page then turn on the Generate netlist for functional simulation, this would generate vho script similar to rtl.You can also maintain the hierarchy by turning the function on.

    This will not generate the .sdo file for the design hence delays would not be used in the vho file.

    Hope that works!!

    This also generates a automated script(.tcl script) to generate quartus compatible vcd file which is a huge script depending on your design, I have never used this script to generate vcd fie instead I have generated my own script.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    so wouldn't an RTL VCD match a gate level VCD without timing information (and be faster to simulate)?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    An RTL simulation would not give as accurate power estimation because all of the internal nodes/routing don’t exist in RTL.

    So rtl vcd will no have all the internal nodes/routing information.

    Also I have tried to compare vcd file for both rtl and gate level and the signals captured by rtl is approx 10-20% of signal captured by gate level simulation.

    In my dummy design toggle rate for 126 signals were captured by rtl and 1540 by gate level simulation in their respective vcd files

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    ok that makes sense. i was under the impression that the VCD you feed to Powerplay only needs top level signals, but maybe that was just to save space at the expense of less accurate results.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I got similar results when I use the RTL level simulation (10% usage from simulation file, and rest on default of toggle rate of 12.5%).

    I did use the tcl file from Altera to gather my vcd but its the same as doing the command vcd add -r /dut/* on modelsim.

    Thanks mehakchopra, I think what you suggest on functional setting will solve my issue of non-matching sim results.

    Good luck on your end.

    Thanks,

    -pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi, I'm having touble with the PowerPlay tool in Quartus II. I'm a beginner to this software. I have generated the reqd vwf , vcd and saf files but when i run the PowerPlaytool i keep getting an error saying ' Successful run of Assembler reqd' . I the run the fitter and assembler from the processing/start menu , but i still receive the same error. I would be greatful if you could help me .

    Thank You.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Try running the entire Build Process, once the design is fitted and built , you have the option to invoke the Power Analyzer tool and this is where you import vcd and all your toggle statistics.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    To test the power play and to make sure I was doing this right, I worte a simple two bit adder code. The operand "a" incerements every four cycles on the pos edge of a clk whiile "b" counts form 0 to 3 and wraps back on the same clk. I am using the .vo file to run my simulation in modelsim, but the confidence level is still low.I source the dump_all_vcd_nodes.tcl file to get the signal activity when I run the simulation. Do I change my test bench for the simulation with .vo file? I wrote the test bench and tested it on the .v files and the wave form looks good. Am I missing something here. Please help :confused: