Honored Contributor
Honored ContributorHi,
To avoid the timing issues you need to change the settings, do the following steps to change the settings 1)Assignments > Settings 2)EDA Tool Settings > Simulation 3) On the page check Generate VCD file script (optional step) 4) Go to More Settings on the same page then turn on the Generate netlist for functional simulation, this would generate vho script similar to rtl.You can also maintain the hierarchy by turning the function on. This will not generate the .sdo file for the design hence delays would not be used in the vho file. Hope that works!! This also generates a automated script(.tcl script) to generate quartus compatible vcd file which is a huge script depending on your design, I have never used this script to generate vcd fie instead I have generated my own script.
