Error : object used but not declared

Question

Hi,

I just want to create a signal_copie_req out std_logic :

entity test_connexions is

port(

signals ...

signal_copie_req : out_std_logic;

)...

COMPONENT test_connexions

PORT(

signals ...

signal_copie_req : out_std_logic;

)...

i_test_connexions : test_connexions

PORT MAP (

signals ...

signal_copie_req => signal_copie_req,

)...

but I have this error that I don't understand :

Error (10482): VHDL error at top_fpga_opg_master.vhd(3158): object "signal_copie_req" is used but not declared

Error (10558): VHDL error at top_fpga_opg_master.vhd(3158): cannot associate formal port "signal_copie_req" of mode "out" with an expression

Does anyone knows how to solve this problem ?

Thanks

altera_forum · Answer

signal_copie_req =&gt; signal_copie_req -- Error is here

altera_forum · Answer

--- Quote Start ---

entity test_connexions is

port(

signals ...

signal_copie_req : out_std_logic;

)...

--- Quote End ---

is this in your code, or is it "out std_logic;"

or

if there is the right one, then check the name of your entity, because the entity declares a component with its own name...

altera_forum · Answer

Or I don't understand what you are doing because it's only parts of you whole code.

Or you don't understand what a signal in VHDL means.

As taz said there should be a space between out and std_logic.

Also there should not be a , or ; at the end of a port or portmap.

This code is really confusing this way, just past you entity, component and portmap as a whole.

altera_forum · Answer

yep that was it "out_std_logic", sorry to give a piece of code and not the whole code like I wrote in my VHDL project. Regards, Julien_92.

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