Error : object used but not declared

Or I don't understand what you are doing because it's only parts of you whole code.

Or you don't understand what a signal in VHDL means.

As taz said there should be a space between out and std_logic.

Also there should not be a , or ; at the end of a port or portmap.

This code is really confusing this way, just past you entity, component and portmap as a whole.