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I am afraid that you will have to step up to MAX-10 to get DDR IO.
I checked the MAX-V data-sheet/handbook and couldn't find a reference to DDR IO operation.
I you want to use MAX-V (or MAX-II) you better use a clock with twice the bit-rate, which should pose no issue for SDIF-3 speeds
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That was exactly what I thought in the very early days. Since the design features an external Master clock oscillator, which is used by the ADC chip as well, to derive it's DSD bit clock by dividing it, so thinking of doing the same for the double-data rate CLK to govern the CPLD global clock port, input the MCLK, then use CLKDIV2 for DSD128 (2x dsd), or CLKDIV4 for standard 1xDSD.
I was thinking of using 2 DFFs, the first one providing the first non-inverted
'semi-bit, the second one for the inverted semi-bit.
The thing is that I don't know how these 2 FFs can be put in succession to complete the pattern.
Any hint? :confused:
Thanks.
Honored Contributor
