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Thank you for the quick reply.
Unfortunately my code cannot be synthesized. I get the following error:
"[Synth 8-27] nested clocked statements not supported [encoder1.vhd":27]
What I wanted to get was: at rising edge, the first semi-bit of pattern, at the falling edge, the second semi-bit (inverted) of pAttern.
Is there a better way to do it?
If you can help, that would be fantastic.
My code is attached to my first message.
Thanks.
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If you properly format you code you see immediately why:
SENSE_CLK : process(clk) is
begin
if (clk'EVENT and clk = '1') then --detect source data @ rising edge
q0 <= data_l;
q1 <= data_r;
if (clk'EVENT and clk = '0') then
q0 <= not data_l;
q1 <= not data_r;
end if;
end if;
end process SENSE_CLK;
Hint: try using an
elsif Another hint: consider using a
ddr output element
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