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Altera_Forum
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8 years ago

Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie

Hello folks, I'm a newbie in VHDL programming. I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip. The dsd stream from the chip features two...
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Altera_Forum
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8 years ago

Thank you for the quick reply.

Unfortunately my code cannot be synthesized. I get the following error:

"[Synth 8-27] nested clocked statements not supported [encoder1.vhd":27]

What I wanted to get was: at rising edge, the first semi-bit of pattern, at the falling edge, the second semi-bit (inverted) of pAttern.

Is there a better way to do it?

If you can help, that would be fantastic.

My code is attached to my first message.

Thanks.