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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

emif ref clock constraint

clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
Timing
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I'm not really sure about that but can you share the design file that I can replicate it at my end?

I can try to check if there is any cause for the EMIF IP to not state the ref_clk as a master clock.

You can send it through Private Message if you're not comfortable to share it in this public forum.


Regards,

Adzim