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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

emif ref clock constraint

clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
Timing
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Does the emif_usr_clk is exported or connect to any other clock input port?


Can you share some snapshot of the SDC File Lists and Clocks from the Timing Analyzer GUI?


Regards,

Adzim


  • CosmoKramer's avatar
    CosmoKramer
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    nope. emif_usr_clk should be generated within the emif ip. I see all the generated clocks from the ip are in the "ignored sdc assignments" list. I have two instances of this ip. Does that cause any issues? it is ignored list because "ip did not find a master clock though it thinks ref_clk as potential master clock". Any reason why tool did not use ref_clk as master clock?