Forum Discussion
CosmoKramer
Occasional Contributor
Occasional Contributoremif ref clock constraint
clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
CosmoKramerOccasional Contributor
Occasional ContributorI tried to find "emif_usr_clk" port on the emif ip but name finder does not show anything similar to it. And I do not see any generated clocks from ref_clk.
