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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

emif ref clock constraint

clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Just create a clock constraint for user_clk_a as usual. You can use the Name Finder in the timing analyzer GUI to find the correct target. Then use create_clock_group as usual.