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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

emif ref clock constraint

clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
Timing
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


By right Quartus will auto generate the clock signal name and you don't have to worry about it.

You can verify again in Timing Analyzer for the clock generated by Quartus in TA > Tasks > Clocks > Report Clocks.

If clk_a and usr_clk_a are found out asynchronously, you can straight away set the constraint without creating anymore clock.


Regards,

Adzim