Forum Discussion
CosmoKramer
Occasional Contributor
Occasional Contributoremif ref clock constraint
clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to bunch of other logic on the fabric. I have a create_clock command for clk_a: create_clock -name ...
sstrell
Super Contributor
Super ContributorThe clock is connected directly to a PLL by the IP so it knows the clock speed based on the parameter settings in the IP and builds a .sdc based on that. So you don't need to add an extra constraint for this.
CosmoKramerbut clk_a is used elsewhere in the design so I will need to have constraint for it. user_clk_a is also used elsewhere in the design, i will need a constraint for this as well.
lastly clk_a, user_clk_a should be added to asynchronous group.
how should i constraint clk_a and user_clk_a ? I am not sure how to create clocks for these to clocks as I do not know how these clocks are named by the tool.
