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Altera_Forum
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14 years ago

Embedded Multiplier vs Logic Elements

Hi everybody, I have a question on the synthesis of a multiplier written in VHDL. I have a module (in VHDL) which uses several multipliers. But when I run the Quartus compilation, thoses m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can set a synthesis attribute on architecture level. Follow the description in the Quartu software handbook. 

architecture rtl of MyUnit is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";