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Altera_Forum's avatar
Altera_Forum
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8 years ago

Efficiency improvements after switching to 17.1 from 17.0

Just as an FYI: I noticed significant resource savings on the same code when switching to version 17,1 of the tool from version 17.0. I'm not sure if this is common for new releases of this tool but thought I should mention it. If you're getting tight on resources it may be worthwhile to install 17.1 alongside whatever version you're using and try it out. (Note: don't forget to use a BSP that supports 17.1).

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  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I have same question about difference between 17.1 and 17.0

    When I emulating a kernel and get the event time, in 17.0 the time will be equal to system clock time like:

    event time: 95xxx ms

    sys time: 95xxx ms

    But in 17.1, it will be different, like:

    event time: 3xx ms

    sys time: 95xxx ms

    Is this because that event time in 17.1 only count simulated execution time ?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    If you are experiencing that behavior on the exact same kernel, you should consider reporting it to Altera since it might be a bug. However, execution time or event time during simulation do not represent anything meaningful; i.e. lower emulation time on a kernel does not mean it will also be faster on the FPGA. Hence, you should avoid drawing any conclusions based on simulation time.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

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    Anyone tried the new "host channels" feature?

    --- Quote End ---

    I'd like to, but it is only available in the BSP of Altera's reference board, while I use a different board. I don't think any other board supports it right now.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I believe that host channels are only used for supporting emulating io channels from fpga to fpga via Linux named pipes or files on the host. This way, emulating io channels and host channels are essentially the same thing (except named pipes is a Linux only feature). This is supported at least since 17.0 I believe and works well for emulating a multi fpga solution using io channels in my experience.

    The new thing that's been added in 17.1 is the "host pipes" which allow for communication between the host and kernel directly, outside of emulation. One of the boards I'm using has 17.1 bsp support from Nallatech which hopefully I can find some time to work on soon.