Effect of ROM port width of LE usage?

I'm trying to keep things general so as to not get tied up in code questions. I'm not really concerned with syntax or anything, but the basic architecture, is that I have a bunch of static, fixed data, split into 237 bit chunks. I'm accepting input from the outside world. Each input has to be checked against every 237 bit chunk doing some relatively straightforward linear algebra. Each of these tests requires something like 24 multipliers, so I can't implement as many functional units as I have 237 bit chunks onto the FPGA. So my goal is to implement as many as I can, and then when input comes in, do the computation, then load in the next 237 bits and check the same input against it, etc., until all 237 bit chunks have been checked. This is all unimportant, but my point is, at compile time I have a large number of 237 bit chunks of data. This data is fixed, static, and not changing. My question is is there an easy way to load 237 bits at a time from one of the memory systems, or if I'll need to do this over a number of cycles 16 bits at a time, or if there's a better way to do this.