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It sounds like it's using the LEs as LUT Ram. Why do you need such a wide bus?
is it synchronous? have you tried attributes to put it into M4Ks?
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Basic idea is I'm implementing a certain number of functional units on the FPGA. The number I can fit isn't sufficient to completely parallelize my process, so I'm multiplexing them. Each unit has a certain amount of fixed data associated with it, so let's say I can fit 50 of the board, but I need 100 computations done. So for a given input, I need to load the fixed data for the 50 funtional units on the board, latch it into flip flops, do the computation with the input, then load the fixed data for the other 50 that don't fit, and do the computation on the same input. 237 bits just happens to be the amount of fixed data for a given functional unit. I guess I could just make a smaller port width and have the transfer take a few cycles. Is that how something like this would normally be done?
Thanks!
Honored Contributor
