Edge detection asynchronous signal fails

Are you simulating the code or the post place and route netlist? This would be normal in the netlist as the tracks for each bit will be different lengths. As long as they dont violate the setup/hold times in timequest it will be ok.

This assumes that my_input and data_ready are synchronised to the clock domain. Using asynchronous signals will cause bad glitches.

Note: in your testbench you are using absolute time delays - I recommend synchronising your testbench to your clock otherwise you might get delta problems if any input aligns with the clock.