Edge detection asynchronous signal fails

Thanks both for your replies. I changed my code (see below) so it works on a rising_edge of a clock input and also removed the else statement since I got glitches on my_output. Seems like my_output was changed to quick. It works now

A follow up question to @Tricky comment: how do concurrent statements outside a process work then? Don't say also assume that the values are ready from 0s? e.g.

my_output <= '111111111' when data_ready = '1';

Or would i use the after statement here?

Changed code of the original question:(working now):

entity mul is port(
	clk			: in std_logic;
	my_input 	: in std_logic_vector( 7 downto 0 );
	data_ready 	: in std_logic;
	my_output	: out std_logic_vector( 8 downto 0 )
);
end mul;
architecture behavior of mul is
	signal previous_value : std_logic := '0';
begin	
	mul_2 : process( clk )
	begin
		if rising_edge( clk ) then
			previous_value <= data_ready;							   -- set previous value
			if data_ready = '1' AND previous_value = '0' then				-- detect rising edge
				my_output <= my_input(7 downto 0) & "0";		-- mul by 2, shift left
			end if;
		end if;
	end process;					
end behavior;	

Testbench:

BEGIN                                                        
        -- code that executes only once                      
	data_ready <= '0';
	my_input <= "11100011";  -- expected output 111000110
	wait for 200ns;
	
	data_ready <= '1';
	wait for 200ns;
	
	data_ready <= '0';
	my_input <= "00110011";
	wait for 200ns;
	
	data_ready <= '1';		
	wait for 200ns;
WAIT;                                                       
END PROCESS init;    
                                       
-- clock generation - 50MHz
process
begin
  clk <= '1';
  wait for 10 ns;
  clk <= '0';
  wait for 10 ns;
end process;  

Cheers and thanks.